To save precious layout space or increase interconnection efficiency, multiple chips of integrated circuits (ICs) can be stacked together as a single IC package. To that end, a three-dimensional (3D) stack packaging technology is used to package the chips of integrated circuits. Through-silicon vias (TSVs) are widely used to accomplish the 3D stack packaging technology. A through-silicon via is a vertical conductive via completely passing through a silicon wafer, a silicon board, a substrate of any material or die. Nowadays, the 3D integrated circuit (3D IC) technology is applied to a lot of fields such as memory stacks, image sensors or the like.
Usually manufacturing a single chip of integrated circuits involve more than several hundred steps and failure of one of the steps or a tiny particle on the chip would destroy the chip. Applying 3-D integrated circuit (3D IC) technology does not make this situation better but worse due to much more extra steps needed, so there is a need to increase the fault tolerance of a chip thereby increasing the yield of a wafer.